1. Field of the Invention
The present invention relates to a method for manufacturing a component, in particular a microelectromechanical component, having a through-connection.
2. Description of the Related Art
The development of increasingly smaller packets of microelectromechanical components (MEMS, microelectromechanical system) requires, among other things, stacking and through contacting of individual elements such as a sensor, a sensor cap, and an evaluation circuit (ASIC). Arranging the elements one on top of the other is referred to as MEMS 3D integration. The so-called through silicon vias (TSV) are one option for a through-connection in microelectromechanical components built up on silicon substrates. Such TSV structures must meet a number of criteria concerning their electrical resistance and mechanical stability. In the stacking of various microcomponents such as sensors and ASICs, it is particularly important, among other things, to lead the sensor signal from a capped sensor, for example an acceleration sensor or yaw rate sensor, through the sensor cap.
In implementing vertical contacts, the aim is to achieve contact structures having the smallest possible base area, and at the same time having the lowest possible volume resistance.
To achieve this, very narrow holes having practically vertical walls are generally provided in the semiconductor substrate, for example using a customary trench method or a laser. After the subsequent deposition of an insulating layer and opening the insulating layer at the base of the holes, the holes are completely or partially filled with a metal.
Gas deposition processes such as copper chemical vapor deposition (CVD), or electroplating processes such as copper electroplating deposition, among others, are used for metal plating electrical through-connections in substrates. However, these standard processes are not suited for metal plating a through-connection in the cap of an already capped sensor wafer, since the bonding layer may be attacked by the electroplating baths used, and which may flow through the bonding layer. In contrast, copper CVD processes allow only copper wetting of the side wall, but not complete filling of the contact hole. In addition, these processes use polymer or oxide layers as an insulating layer, which due to their small thickness facilitate parasitic capacitances between the through-connection and the surrounding semiconductor material. The strict requirements for an MEMS via are often not met due to these parasitic capacitances.